 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| www..com M74DW66500B 2x 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 32Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product PRELIMINARY DATA FEATURES SUMMARY MULTIPLE MEMORY PRODUCT - Two 64Mbit (8M x8 or 4M x16), Multiple Bank, Page, Boot Block, Flash Memories - 32Mbit (2M x 16) Pseudo Static RAM SUPPLY VOLTAGE - VCCF = VCCP = 2.7 to 3.3V - VPPF = 12V for Fast Program (optional) Figure 1. Package FBGA ACCESS TIME: 70, 90ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE - Manufacturer Code: 0020h - Device Code: 227Eh + 2202h + 2201h LFBGA73 (ZA) 8 x 11.6mm EACH FLASH MEMORY ASYNCHRONOUS PAGE READ MODE .com - Page Width: 4 Words - Page Access: 25, 30ns - Random Access: 70, 90ns PROGRAMMING TIME - 10s per Byte/Word typical - 4 Words/ 8 Bytes at-a-time Program DataShee VPP/WP PIN for FAST PROGRAM and WRITE PROTECT TEMPORARY BLOCK UNPROTECTION MODE COMMON FLASH INTERFACE - 64 bit Security Code EXTENDED MEMORY BLOCK - Extra block used as security block or to store additional information MEMORY BLOCKS - Quadruple Bank Memory Array: 8Mbits + 24Mbits + 24Mbits + 8Mbits - Parameter Blocks (at both Top and Bottom) DUAL OPERATIONS - While Program or Erase in a group of banks (from 1 to 3), Read in any of the other banks PROGRAM/ERASE SUSPEND and RESUME MODES - Read from any Block during Program Suspend - Read and Program another Block during Erase Suspend 100,000 PROGRAM/ERASE CYCLES per BLOCK PSRAM ACCESS TIME: 70ns UNLOCK BYPASS PROGRAM COMMAND - Faster Production/Batch Programming BYTE CONTROL: UB/LB PROGRAMMABLE PARTIAL ARRAY 8 WORD PAGE ACCESS CAPABILITY: 18ns (max) LOW STANDBY CURRENT: 100A September 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/19 .com DataSheet 4 U .com www..com M74DW66500B TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Input/Output or Address Input (DQ15A-1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash-1 Chip Enable (EF1) and Flash-2 Chip Enable (EF2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Reset/Block Temporary Unprotect (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Chip Enable inputs (E1P, E2P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Upper Byte Enable (UBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Lower Byte Enable (LBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCCF Supply Voltage (2.7 to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCCP Supply Voltage (2.7 to 3.3V). . . . .com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ............... VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FLASH MEMORY DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 t4U.com DataShee MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. Flash DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 7. PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/19 .com DataSheet4 U .com www..com M74DW66500B PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline15 Table 8. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data. . . 16 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 t4U.com .com DataShee 3/19 .com DataSheet4 U .com www..com M74DW66500B SUMMARY DESCRIPTION The M74DW66500B is a low voltage Multiple Memory Product which combines two memory devices; a 64 Mbit Multiple Bank, Boot Block Flash memory (M29DW640D) and a 32 Mbit Pseudo SRAM. This document should be read in conjunction with the M29DW640D and M69AW048B datasheets. Recommended operating conditions do not allow more than one of the internal memory devices to be active at the same time. The memory is offered in an LFBGA73 (8 x 11.6mm, 0.8 mm pitch) package and is supplied with all the bits erased (set to `1'). Figure 2. Logic Diagram VPP/WP VCCF 22 A0-A21 EF1 EF2 15 DQ0-DQ14 EF1 Table 1. Signal Names A0-A20 DQ0-DQ7 DQ8-DQ14 DQ15A-1 G W VCCF Address Inputs common to the Flash Memory and PSRAM Components Data Inputs/Outputs Data Inputs/Outputs Data Input/Output or Address Input Output Enable Input Write Enable Input Flash Memory Power Supply VPP/Write Protect Ground PSRAM Power Supply Not Connected Internally VPP/WP VSS VCCP NC VCCP Flash Memory Control Functions A21 Address Input common to the two Flash Memory Devices Flash-1 Chip Enable Input Flash-2 Chip Enable Input Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Select t4U.com G W RPF BYTE E1P E2P UBP LBP M74DW66500B DQ15A-1 EF2 .com RPF DataShee RB RB BYTE PSRAM Control Functions E1P, E2P UBP LBP Chip Enable Inputs Upper Byte Enable Input Lower Byte Enable Input VSS AI08514 4/19 .com DataSheet 4 U .com www..com M74DW66500B Figure 3. LFBGA Connections (Top view through package) 1 2 3 4 5 6 7 8 9 10 A NC NC B NC NC NC NC C NC A7 LBS VPP /WP W A8 A11 D A3 A6 UBS RPF E2S A19 A12 A15 E A2 A5 A18 RB A20 A9 A13 A21 F NC A1 A4 A17 A10 A14 EF2 NC G t4U.com H NC A0 VSS DQ1 .com DQ3 DQ4 DQ6 NC A16 NC DataShee DQ13 DQ15 /A-1 BYTE EF1 G DQ9 J E1S DQ0 DQ10 VCCF VCCS DQ12 DQ7 VSS K DQ8 DQ2 DQ11 NC DQ5 DQ14 M NC NC NC NC N NC NC AI08515 5/19 .com DataSheet 4 U .com www..com M74DW66500B SIGNAL DESCRIPTION See Figure 2 Logic Diagram and Table 1,Signal high voltage power supply to reduce the time reNames, for a brief overview of the signals connectquired for Program operations. This is achieved ed to this device. by bypassing the unlock cycles and/or using the multiple Word (2 or 4 at-a-time) or multiple Byte Address Inputs (A0-A21). Address lines A0-A20 Program (2, 4 or 8 at-a-time) commands. The are common inputs for the Flash Memory and Write Protect function provides a hardware methPSRAM components. Address line A21 is an input od of protecting the four outermost boot blocks that is common for the two Flash Memory compo(two at the top, and two at the bottom of the adnents. The Address Inputs select the cells in the dress space). memory array to access during Bus Read operations. During Bus Write operations they control the When V PP/Write Protect is Low, VIL, the memory protects the four outermost boot blocks; Program commands sent to the Command Interface of the and Erase operations in these blocks are ignored internal state machine. The Flash memory is acwhile VPP/Write Protect is Low, even when RPF is cessed through the Chip Enable (EF) and Write Enable (W) signals, while the PSRAM is accessed at VID. through two Chip Enable signals (E1S and E2S) When VPP/Write Protect is High, VIH, the memory and the Write Enable signal (W). reverts to the previous protection status of the four Data Inputs/Outputs (DQ0-DQ7). The Data I/O outermost boot blocks (two at the top, and two at outputs the data stored at the selected address the bottom of the address space). Program and during a Bus Read operation. During Bus Write Erase operations can now modify the data in these operations they represent the commands sent to blocks unless the blocks are protected using Block the Command Interface of the Program/Erase Protection. Controller. When V PP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode. Data Inputs/Outputs (DQ8-DQ14). The Data I/O When V PP/Write Protect returns to VIH or VIL noroutputs the data stored at the selected address mal operation resumes. During Unlock Bypass during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not Program operations the memory draws IPP from used and are high impedance. During Bus Write the pin to supply the programming circuits. See the operations the Command Register does not use description of the Unlock Bypass command in the .com these bits. When reading the Status Register Command Interface section. The transitions from these bits should be ignored. VIH to V PP and from V PP to VIH must be slower than tVHVPP. See the M29DW640D datasheet for Data Input/Output or Address Input (DQ15A- more details. 1). When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory BYTE is Low, VIL, this pin behaves as an address pin; DQ15A-1 Low will select the LSB of the admay be left in an indeterminate state. dressed Word, DQ15A-1 High will select the MSB. The VPP/Write Protect pin must not be left floating Throughout the text consider references to the or unconnected or the device may become unreliData Input/Output to include this pin when BYTE is able. A 0.1F capacitor should be connected beHigh and references to the Address Inputs to intween the V PP/Write Protect pin and the VSS clude this pin when BYTE is Low except when Ground pin to decouple the current surges from stated explicitly otherwise. the power supply. The PCB track widths must be sufficient to carry the currents required during Flash-1 Chip Enable (EF1) and Flash-2 Chip Enable (EF2). The Chip Enable input activates the Unlock Bypass Program, I PP. memory to which it is attached, allowing Bus Read Reset/Block Temporary Unprotect (RPF). The and Bus Write operations to be performed. When Reset/Block Temporary Unprotect pin can be Chip Enable is High, VIH, all other pins are igused to apply a Hardware Reset to the memory or nored. to temporarily unprotect all Blocks that have been Output Enable (G). The Output Enable, G, conprotected. trols the Bus Read operation of the Flash Memory Note that if V PP/WP is at VIL, then the two outerand PSRAM components. most boot blocks will remain protected even if RPF is at VID. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the Flash Memory and A Hardware Reset is achieved by holding Reset/ PSRAM components. Block Temporary Unprotect Low, V IL, for at least VPP/Write tPLPX. After Reset/Block Temporary Unprotect VPP/Write Protect (VPP/WP). The Protect pin provides two functions. The VPP funcgoes High, V IH, the memory will be ready for Bus tion allows the Flash memory to use an external Read and Bus Write operations after tPHEL or 6/19 t4U.com DataShee .com DataSheet 4 U .com www..com M74DW66500B tRHEL, whichever occurs last. See the gardless of the level of E1P. E1P and E2P can also M29DW640D datasheet for more details. be used to control writing to the PSRAM memory array, while WP remains at VIL. It is not allowed to Holding RPF at VID will temporarily unprotect the set EF1 or EF2 at VIL, E1P at VIL and E2P at V IH at protected Blocks in the memory. Program and the same time. Erase operations on all blocks will be possible. PSRAM Upper Byte Enable (UBP). The Upper The transition from VIH to VID must be slower than tPHPHH. Byte Enable input enables the upper byte for PSRAM (DQ8-DQ15). UBP is active low. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify PSRAM Lower Byte Enable (LBP). The Lower Byte Enable input enables the lower byte for when the Flash memory is performing a Program PSRAM (DQ0-DQ7). LBP is active low. or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is VCCF Supply Voltage (2.7 to 3.3V). VCCF prohigh-impedance during Read mode, Auto Select vides the power supply for Flash memory operamode and Erase Suspend mode. tions (Read, Program and Erase). After a Hardware Reset, Bus Read and Bus Write The Command Interface is disabled when the operations cannot begin until Ready/Busy beVCCF Supply Voltage is less than the Lockout Voltcomes high-impedance. age, VLKO . This prevents Bus Write operations from accidentally damaging the data during power The use of an open-drain output allows the Ready/ up, power down and power surges. If the Program/ Busy pins from several memories to be connected Erase Controller is programming or erasing during to a single pull-up resistor. A Low will then indicate this time then the operation aborts and the memothat one, or more, of the memories is busy. ry contents being altered will be invalid. Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to A 0.1F capacitor should be connected between switch between the x8 and x16 Bus modes of the the VCCF Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power Flash memory. When Byte/Word Organization Sesupply. The PCB track widths must be sufficient to lect is Low, V IL, the Flash memory is in x8 mode, when it is High, V IH, the Flash memory is in x16 carry the currents required during Program and mode. Erase operations, ICC3. The VCCP Supply Voltage (2.7 to 3.3V). VCCP proPSRAM Chip Enable inputs (E1P, E2P). .com Chip Enable inputs activate the PSRAM control vides the power supply for the PSRAM. logic, input buffers and decoders. E1 P at VIH with VSS Ground. VSS is the ground reference for all E2P at VIH deselects the memory, reducing the voltage measurements in the Flash and PSRAM power consumption to the standby level, whereas chips. E2P at VIL deselects the memory and reduces the power consumption to the Power-down level, re- t4U.com DataShee 7/19 .com DataSheet 4 U .com www..com M74DW66500B FUNCTIONAL DESCRIPTION The Flash Memory and PSRAM components have a common power supply. The components are distinguished by four chip enable inputs: EF1 for one Flash memory, EF2 for the other, and E1S and E2S for the PSRAM. Recommended operating conditions do not allow more than one of the Flash Memory or PSRAM component to be in active mode at the same time. Table 2. Main Operation Modes Operation Mode(3) Read Flash Memory 1 Write Output Disable Standby Reset Read Flash Memory 2 Write Output Disable Standby Reset Read PSRAM Write Output Disable Standby Deep Power Down EF1 VIL VIL X VIH X VIH VIH VIH VIH VIH EF2 VIH VIH VIH VIH VIH VIL VIL X VIH X RPF VIH VIH VIH VCC 0.3 VIL VIH VIH G VIL VIH VIH X X VIL VIH W VIH VIL VIH X X VIH VIL Flash Memory 1 and PSRAM must both be in Standby Flash Memory 2 Data Output Flash Memory 2 Data Input Any Flash Memory 2 or PSRAM mode is allowed Flash Memory 1 Hi-Z E1P E2P UBP, LBP(2) DQ15-DQ0 Flash Memory 1 Data Output Flash Memory 1 Data Input The most common example is simultaneous read operations on the Flash Memory and PSRAM components which would result in a data bus contention. Therefore it is recommended to put two of the components in the high impedance state when reading from the third (see Table 2 Main Operation Modes for details). Flash Memory 2 and PSRAM must both be in Standby t4U.com VIH .com VIH VIH VCC 0.3 VIL X X VIL VIH VIH X X X X VIH VIL VIH X X VIL VIL VIL VIH X VIH VIH VIH VIH VIL VIL VIL X X X PSRAM Hi-Z PSRAM Data Output PSRAM Data Input Any Flash Memory 1 or PSRAM mode is allowed Flash Memory 2 Hi-Z DataShee Both Flash Memories must be in Standby Any One Flash Memory mode is allowable Note: 1. X = Don't Care (V IL or VIH). 2. UB P and LBP are tied together. 3. This table is valid when BYTE = VIH. This table is also valid when BYTE = VIL , with the only difference that DQ15-DQ8 are always high impedance when the Flash Memory components are being accessed. 4. For the Block Protect and Unprotect features, refer to the M29DW640D datasheet. Only the In-System Technique is available in the stacked product. 5. To read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Block indicator bit, refer to the "Auto Select Command" in the M29DW640D datasheet. 8/19 .com DataSheet 4 U .com www..com M74DW66500B Figure 4. Functional Block Diagram VCCF VPP/WP EF1 64 Mbit Flash Memory 1 RBF W RPF BYTEF G EF2 64 Mbit Flash Memory 2 DQ15/A-1-DQ0 A21 A0-A20 t4U.com .com VDDP DataShee E1P 32 Mbit PSRAM E2P UBP LBP VSS AI08516 9/19 .com DataSheet 4 U .com www..com M74DW66500B FLASH MEMORY DEVICES The M74DW66500B contains two 64Mbit Flash memories. For detailed information on how to use these, see the M29DW640D datasheet, which is available on the STMicroelectronics web site, www.st.com. PSRAM DEVICE The M74DW66500B contains a 32Mbit Pseudo SRAM. For detailed information on how to use it, see the M69AW048B datasheet, which is avail- able from your local STMicroelectronics distributor. t4U.com .com DataShee 10/19 .com DataSheet 4 U .com www..com M74DW66500B MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 3. Absolute Maximum Ratings Value Symbol TA TBIAS TSTG VIO VCCF VID VPPF VCCP Parameter Min Ambient Operating Temperature (1) Temperature Under Bias Storage Temperature Input or Output Voltage Flash Supply Voltage Identification Voltage Program Voltage PSRAM Supply Voltage -40 -50 -65 -0.5 -0.6 -0.6 -0.6 -0.5 Max 85 125 150 VCCF +0.3 4 13.5 13.5 3.6 C C C V V V V V Unit plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Note: 1. Depends on range. t4U.com .com DataShee 11/19 .com DataSheet 4 U .com www..com M74DW66500B DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. The operating and AC measurement parameters given in this section (see Table 4 below) correspond to those of the stand-alone Flash Memory and PSRAM components. For compatibility purposes, the M29DW640D voltage range is restricted to VCCS in the stacked product. Table 4. Operating and AC Measurement Conditions Flash Memories Parameter Min VCCF Supply Voltage VCCS Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 0 to VCCF VCCF/2 2.7 - -40 30 10 0 to VCCP VCCP/2 Max 3.6 - 85 Min - 2.7 -30 30 5 Max - 3.3 85 V V C pF ns V V PSRAM Units t4U.com Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit .com VCCF VCCF VCCF/2 0V AI08186 DataShee VPP VCCF 25k DEVICE UNDER TEST 0.1F 0.1F CL 25k CL includes JIG capacitance AI08187 Table 5. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V, f=1 MHz VOUT = 0V, f=1 MHz Typ Max 12 15 Unit pF pF Note: Sampled only, not 100% tested. 12/19 .com DataSheet 4 U .com www..com M74DW66500B Table 6. Flash DC Characteristics Symbol ILI ILO ICC1(2) ICC2 Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) Test Condition 0V VIN VCC 0V VOUT VCC EF = VIL, G = VIH, f = 6MHz EF = VCC 0.2V, RPF = VCC 0.2V Program/Erase Controller active VPP/WP = VIL or VIH VPP/WP = VPP VIL VIH VPP IPP VOL VOH VID Input Low Voltage Input High Voltage Voltage for VPP/WP Program Acceleration Current for VPP/WP Program Acceleration Output Low Voltage Output High Voltage Identification Voltage Program/Erase Lockout Supply Voltage VCC = 3.0V 10% VCC = 3.0V 10% IOL = 1.8mA IOH = -100A VCC -0.4 11.5 12.5 2.3 -0.5 0.7VCC 11.5 Min Max 1 1 10 100 20 20 0.8 VCC +0.3 12.5 15 0.45 Unit A A mA A mA mA V V V mA V V V V ICC3 (1,2) Supply Current (Program/ Erase) t4U.com VLKO .com 1.8 DataShee Note: 1. Sampled only, not 100% tested. 2. In Dual operations the Supply Current will be the sum of I CC1(read) and I CC3 (program/erase). 13/19 .com DataSheet 4 U .com www..com M74DW66500B Table 7. PSRAM DC Characteristics Symbol ICC1 VCC Active Current ICC2 Parameter Test Condition VCC = 3.3V, VIN = VIH or VIL, E1 = VIL and E2 = VIH, IOUT = 0mA tRC / tWC = minimum tRC / tWC = 1 s Min Max 30 3 Unit mA mA ICC3 VCC Page Read Current VCC = 3.3V, VIN = VIH or VIL, E1 = VIL and E2 = VIH, IOUT = 0mA, tPRC = min. Sleep 10 mA ICCPD ICCP4 ICCP8 ICCP16 ICCS ILI ILO ISB VIH (1) VIL (2) VOH VOL VCC Standby Current Input Leakage Current Output Leakage Current Standby Supply Current CMOS Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage VCC Power Down Current VCC = 3.3V, VIN = VIH or VIL, E2 0.2V 10 40 50 65 1.5 -1 -1 1 1 100 0.8VCC -0.3 VCC + 0.2 0.2VCC A A A A mA A A A V V V 4M partial 8M partial 16M partial VCC = 3.3V, VIN = VIH or VIL, E1 = E2 = VIH 0V VIN VCC 0V VOUT VCC VCC = 3.3V, VIN 0.2V or VIN VCC -0.2V, E1 = E2 VCC -0.2V t4U.com .com VCC = 2.7V, IOH = -0.5mA IOL = 1mA DataShee 1.4 0.4 V Note: 1. Maximum DC voltage on input and I/O pins is VCC + 0.2V. During voltage transitions, input may positive overshoot to VCC + 1.0V for a period of up to 5ns. 2. Minimum DC voltage on input or I/O pins is -0.3V. During voltage transitions, input may positive overshoot to VSS + 1.0V for a period of up to 5ns. 14/19 .com DataSheet 4 U .com www..com M74DW66500B PACKAGE MECHANICAL Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline D FD FE SD D1 E E1 SE BALL "A1" t4U.com e A .com b A2 A1 DataShee ddd BGA-Z50 Note: Drawing is not to scale. 15/19 .com D a t 4.hee a US c o m t www..com M74DW66500B Table 8. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 11.600 8.800 0.800 0.400 1.400 0.400 0.400 - - - - - - 11.500 0.910 0.400 8.000 7.200 0.100 11.700 0.4567 0.3465 0.0315 0.0157 0.0551 0.0157 0.0157 - - - - - - 0.4528 0.350 7.900 0.450 8.100 0.250 0.0358 0.0157 0.3150 0.2835 0.0039 0.4606 0.0138 0.3110 0.0177 0.3189 Min Max 1.400 0.0098 Typ Min Max 0.0551 inches t4U.com .com DataShee 16/19 .com DataSheet 4 U .com www..com M74DW66500B PART NUMBERING Table 9. Ordering Information Scheme Example: Device Type M74 = MMP (Flash + PSRAM) Architecture D = Dual Operation Operating Voltage W = VCCF = VCCP = 2.7V to 3.3V Flash Memory 1 Device Size (Die1 Density) 6 = 64 Mbit Flash Memory 2 Device Size (Die2 Density) 6 = 64 Mbit PSRAM Device Size (Die3 Density) 5 = 32 Mbit Die4 0 = none present Flash Memory Specification Details 0 = Multiple Bank Stacked Specification Details B=0.15m Flash Memory and 0.18m PSRAM Speed 70 = 70ns 90 = 90ns Package and Temperature Range Z = LFBGA73: 8 x 11.6mm, 0.8mm pitch Option T = Tape & Reel packing M74DW 6 6 5 0 0 B 70 ZT t4U.com .com DataShee Note: This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest ST sales office. Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 17/19 .com DataSheet 4 U .com www..com M74DW66500B REVISION HISTORY Table 10. Document Revision History Date 19-May-2003 24-Sep-2003 Version 1.0 1.1 First Issue Voltage supply range extended 2.7V working at all speed options Revision Details t4U.com .com DataShee 18/19 .com DataSheet 4 U .com www..com M74DW66500B t4U.com .com Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 19/19 .com DataSheet 4 U .com |
Price & Availability of M74DW66500B
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |